The high quality and the relevance of Chaimae’s thesis contributed to get significant results as a part of ROBUSTESSE project.
About this thesis
Therefore, for the integrated circuits dedicated to embedded applications, it is necessary to study the different aspects of EMC modeling as well as the reliability the modeling. These last years, several standards have been proposed for the construction of predictive EMC models such as ICEM-CE/RE (Integrated Circuit Emission Model for Conducted and Radiated Emission) and ICIM-CI (Integrated Circuit Immunity Model for Conducted Immunity). On the other hand, to integrate the effect of aging in EMC models, it is important to study the main intrinsic degradation mechanisms that accelerate the aging of ICs, such as HCI (Hot Carrier Injection), TDDB (Time Dependent Dielectric Breakdown), EM (Electromigration) and NBTI (Negative Bias Temperature Instability). For this purpose, there are existing models for the reliability prediction, such as the MIL-HDBK-217 standard and the FIDES standard. However, these models could take into account only the activation of one degradation mechanism. The combination of several degradation mechanisms could be critical for the IC performances and could contribute in the evolution of EMC level.
This thesis deals with the construction of a conducted emission model of an FPGA and the proposition of new modeling methodologies. Furthermore, the reliability of the tested FPGA is described using a new predictive model, which takes into account the activation of the different degradation mechanisms. The reliability model has been combined with the EMC model for the long-term conducted emission level prediction.
- Mme Sonia BEN DHIA – INSA Toulouse – PhD Advisor
- M. Alexandre BOYER – INSA Toulouse – PhD Co-Supervisor
- M. Fabian VARGAS – Catholic University – PUCRS – Rapporteur
- M. Berand DEUTSCHMAN – Graz University of Technology – Rapporteur
- Mme Geneviève DUCHAMP – Toulouse University – Examiner
- Mme Marise BAFLEUR – LAAS-CNRS – Examiner
- M. Frédéric LAFON – VALEO – Examiner
- M. André DURIER – IRT Saint Exupéry – Examiner
In 2016, Chaimae won the best paper award at global conference on embedded electronics
Last year, Chaimae Ghfiri, was awarded the prize for best paper at the 2016 7th Asia-Pacific International Electromagnetic Compatibility and Signal Integrity Symposium (APEMC) which took place in Shenzhen, China between 18 and 21 May. This exceptional performance recognises the talent of a young researcher. It also highlights a highly successful academic-multi-sector industrial co-supervision put in place thanks to the Institutes of Technology model introduced in 2011. Academic (the University of Toulouse, Insa Toulouse, LAAS-CNRS) and industrial partners (Continental, Airbus) all contributed the work being presented in the winning paper.
Related Publications & Conference Communications
C. Ghfiri, A. Boyer, A. Durier, S. Ben Dhia : “Methodology of modeling of the internal activity of a FPGA for conducted emission prediction purpose”. IEEE (2017)
C. Ghfiri, A. Boyer, A. Durier, S. Ben Dhia, C Marot : “Construction d’un modèle ICEM pour predire l’émission électromagnètique d’un FPGA “. 18e Colloque International et Exposition sur la Compatibilite Electromagnetique (CEM, 2016)
A. Durier, A. Bensoussan, M. Zerarka, C. Ghfiri, A. Boyer and H. Frémont : “A methodologic project to characterize and model COTS component reliability”. Microelectronics Reliability Journal (2015)