Invited lectures

Why Weibull?... Why Not!

Professor Joseph Bernstein, Ariel University, Israël

All reliability professionals are required to report reliability in simple-to-understand yet meaningful metrics. Typically, mean time to fail (MTTF) or defective parts per million (DPPM) are used by many industrial practitioners as a way to communicate the calculated reliability of a product, device or system. Most metrics for reliability assume a constant hazard rate or constant failure rate statistical approach. This is mathematically described as a time invariant Poisson process. This is exactly the “exponential” reliability model as is well known by most industries and is the working assumption when using MTTF or other such metrics.

In reality, everyone knows that some equipment have wearout or fatigue mechanisms that accumulate over time and makes the likelihood of an older product inherently more susceptible to failure than a new piece of equipment. Similarly, companies are constantly working on reliability growth and improvement with each generation making the decision to upgrade implicitly a decision to improve long-term reliability. Also, defects are often seen during product introduction and decreasing failure rates are observed.

This tutorial will focus on the mathematical basis for exponential reliability models and how they are justified by physics of failure and basic assumptions of thermodynamics. The physics and statistics are then extended to justify using the Weibull distribution to describe more accurately the failure distribution in the field. However, this information is often lost in communication since MTTF is not appropriate once the Poisson model is no longer used. Furthermore, Weibull describes both decreasing as well as increasing failure rates and the information contained therein is lost when converted to a single MTTF parameter.

This tutorial will develop the understanding needed in order to decide when it is appropriate and when it is not appropriate to use Weibull statistics as opposed to Poisson statistics. Participants will learn the tools to develop their own insight as to when the MTTF statistic is meaningful and can be used for making proper reliability decisions. Through some simple mathematical formalisms and basic understanding for thermodynamics, participants of this webinar will learn for themselves how Weibull is often a useful measure for describing reliability and how it is often inappropriately used. Our goal will be to clarify any confusion that exists as to the proper way to report reliability using single statistical metrics or when more sophisticated metrics are required.

Reliability Prediction Based on Multiple Accelerated Life Tests.

Professor Joseph Bernstein, Ariel University, Israël

To this day, the users of our most sophisticated electronic systems that include opto-electronic, photonic, MEMS device, etc. are expected to rely on a simple reliability value (FIT) published by the supplier. The FIT is determined today in the product qualification process by use of HTOL or other standardized test, depending on the product. The manufacturer reports a zero-failure result from the given conditions of the single-point test and uses a single-mechanism model to fit an expected MTTF at the operator’s use conditions.

The zero-failure qualification is well known as a very expensive exercise that provides nearly no useful information. As a result, designers often rely on HALT testing and on handbooks such as Fides, Telecordia or Mil Handbook 217 to estimate the failure rate of their products, knowing full well that these approaches act as guidelines rather than as a reliable prediction tool. Furthermore, with zero failure required for the “pass” criterion as well as the poor correlation of expensive HTO data to test and field failures, there is no communication for the designers to utilize this knowledge in order to build in reliability or to trade it off with performance. Prediction is not really the goal of these tests; however, current practice is to assign an expected failure rate, FIT, based only on this test even if the presumed acceleration factor is not correct.

We present, in this tutorial, a simple way to predictive reliability assessment using the common language of Failure In Time or Failure unIT (FIT). We will evaluate the goal of finding MTBF and evaluate the wisdom of various approaches to reliability prediction. Our goal is to predict reliability based on the system environment including space, military and commercial. It is our intent to show that the era of confidence in reliability prediction has arrived and that we can make reasonable reliability predictions from qualification testing at the system level. Our research will demonstrate the utilization of physics of failure models in conjunction with qualification testing using our Multiple – HTOL (M-HTOL) matrix solution to make cost-effective reliability predictions that are meaningful and based on the system operating conditions.

In this seminar, you will learn:

  • understanding of constant-rate failure prediction (MTBF and FIT) ;
  • limitations of the standard Single-Failure-Mechanism approach ;
  • how accelerated tests can be designed for multiple mechanisms ;
  • how multiple-mechanism models can be linearly combined ;
  • how this linear combination can make realistic reliability predictions.

GaN technology for high reliability applications.

Dr. Alex Lidow, CEO EPC (Efficient Power Conversion), USA

Gallium Nitride (GaN) power semiconductors are being adopted in an increasing number of power conversion applications.  The technology is rapidly developing and product experience in the field is expanding. This presentation will begin with a discussion of the state-of-the art in GaN technology, including an overview of GaN technology, GaN transistor structures and the latest electrical performance.

The presentation will continue with a discussion of GaN reliability and major failure mechanisms.  eGaN FETs from Efficient Power Conversion (EPC) have tens of billions of hours of actual field experience with very low failure rates. We will go into detail on the causes of failure and the physics behind EPC’s design-for-reliability process.

Radiation tolerance is a unique attribute of the eGaN FET from EPC and stems from the oxide-free gate structure and the GaN-on-silicon foundation.  We will look at radiation results for total dose and single event upset that confirm the quantum improvement in radiation performance achievable from gallium nitride.

The presentation concludes with a look into future and GaN’s potential to improve performance in existing applications and enable new applications not possible with aging silicon MOSFETs.  Beyond the discrete transistor, the extension of GaN technology to fully integrated circuits will be discussed, furthering the potential of GaN to raise the bar in power conversion performance.

Plenary sessions (oral presentations)

E²CoGaN project – Energy Efficient Converters Using GaN Power Devices

Olivier Crepel, Airbus Group Innovations

E2COGaN target the demonstration of GaN-on-Si as a disruptive high voltage (HV) technology and High Electron Mobility Transistors through the whole value chain up to demonstrators with high industrial, societal and environmental relevance.

In this presentation, a selection of last results will be presented.

Deep submicron reliability issues at CEA Leti

Xavier Garros, CEA Leti (Grenoble, France)

The purpose will be to review the different reliability concerns affecting the sub-100nm CMOS technologies. A general background on the evolution of the reliability issues (TDDB, HCI, NBTI) impacting the transistor will be first presented. They will be correlated to the major technological breakthroughs which occurred from the 65nm node i.e. advent of HK/MG stacks & SiGe channels with performance boosters, change from planar bulk to planar FDSOI or 3D architectures. Then we will focus on NBTI concern. We will show that new developments of ultra-fast measurements techniques were required for an accurate characterization of the ageing and, in turn, of the device lifetime evaluation. Analytical and compact modeling of this phenomenon will also been presented. They are used to predict precisely the effect of NBTI ageing at the circuit level. Finally a new problematic linked to NBTI degradation in nano-scaled transistors called “dynamic variability” will be presented. It will be shown how it can affect the good working of some components of a digital circuit like SRAM memory arrays.

Robustness and reliability assessment of GaN/Si power components: A RTO point of view

Mathieu Gavelle, Hervé Ribot, CEA Leti (Grenoble, France)

As a RTO organization, CEA tech has to demonstrate power GaN-on-Si technology robustness and provide convincing data to industrial partners, before product specifications are defined and for a wide range of applications and industrial qualification standards. This is why we propose a pre-qualification methodology that aims at filling the gap between the early phase of technology development when meeting basic functionalities is still a challenge, and a time when industrial partner can start Product qualification. It is based on:

  • setting up flexible and highly sensitive AC and DC measurements techniques (electrical characterization + industrial power testing), but with sufficient throughput, to produce statistically valid results,
  • conducting robustness testing and “test until failure”,
  • conducting accelerated aging to confirm failure mechanisms and associated activation energies,
  • conducting physical failure analysis,
  • retrofitting all these measurements on design and/or process to mitigate failure mechanisms in an early phase of technological development.

GaN technology for Space application: eeds, constraints and perspectives

Christian Elisabelar & Christian Rouzies, Cnes - Power Chain and Electromagnetic Compatibility Service

Since 2010, CNES made studies on GaN transistor for power applications on space vehicle. Mass, efficiencies and cost are the main drivers to design power converters, GaN can bring many improvements over MOSFET technology.  Increasing the switching frequency can greatly reduce the power supply boards. Other converter topologies best suited for GaN were investigated. But today we are facing the following problems: losses in magnetic circuits limit the rise in frequency, electromagnetic emissions are becoming worrisome and may affect the risk of breaking the GaN transistors.

Moreover, we are looking for qualified GaN power transistor references that are compatible with the space constraints (vacuum, radiation, postponing technologies).

M-STORM reliability model.

Alain Bensoussan (IRT Saint Exupéry, Toulouse, France)

Temperature acceleration failure modes and failure mechanisms are generally based on Arrhenius law and Eyring model which takes into account additional stresses than temperature. The failure mechanisms described in JEDEC JEP122G publication constitute commonly accepted industrial models and are presented in term of stress parameters and/or drift parameter signature mechanisms but they are considering single stress condition, single parameter signature and single failure mechanism at a time. When considering new disruptive technologies for deep submicron integrated circuits, the shrinkage of geometries induces shrinkage of electrical parameter limits and multiple stress induced failures as well as multiple failure mechanisms when operating in harsh environment.

The groundwork of a unified model combining Boltzmann-Arrhenius-Zhurkov (BAZ) from E. Suhir and M-HTOL approaches from J. Bernstein is established and is related to a generalized semiconductor devices reliability model called M-STORM for Multi-phySics mulTi-stressOrs predictive Reliability Model.

It quantifies and predicts the reliability figures of electronic devices when operating under multiple stress as set for Aerospace, Space, Nuclear, Submarine, Transport or Ground application and considering the existence of multiple failure mechanisms activated simultaneously.

ST65nm hardened ASIC technology for Space applications.

Laurent Hili (ESA microelectronics section, Noordwijk, The Netherlands), Florence Malou (Cnes, Toulouse, France), Philippe Roche & Yves Gilot (STMicroelectronics, Grenoble)

The ever increasing electronic miniaturization has deeply changed our daily life with computers, mobile phones and more recently internet of things. While being more conservative the Space sector doesn’t escape to this general trend. However Space electronic has to deal with extra constraints such as extreme temperature range (-55 … +125C), radiation environment and long term reliability (missions profiles up to 20 years). The Deep Sub Micron program initiated by ESA and CNES in 2008, set as a main objective to harden the commercial ST 65nm node and provide European Space industry with a state of the art ASIC technology free of any US export licences (ITAR). Today ST 65nm hardened process (C65SPACE) is “the world most advanced ASIC technology” suitable for Space missions. The current presentation will give an overview of the last 8 years achievements putting the emphasis on hardening activities and features availability (cells, macros) in the final offer. ST C65SPACE technology represents a major leap with respect to the previous generation of hardened ASIC technology (180nm). C65SPACE will therefore allow a major breakthrough in various application domains such as telecom satellites, Rad Hard microprocessors and FPGAs.

Advanced 28 nm UTBB FDSOI CMOS technology in harsh environment impacts and reliability investigation

Philippe Galy, Philippe Roche & Vincent Huard (ST Microelectronics, Grenoble, France)

The 28nm high K metal gate Ultra-thin Body and BOX (UTBB) Fully Depleted SOI (FDSOI) technology has been developed for multiple market segments such as primarily wearable or Internet-of-Things.

This mainstream technology is also an excellent candidate to sustain harsh environments and secure mission-critical applications, targeting automotive, space, avionic, medical and infrastructure/5G.

Those stringent environmental conditions are dominated by radiation, wearout and electrostatic discharge failure modes.

Hence, it is important to accurately characterize the intrinsic resilience of the advanced technology against those aggressors while concurrently developing cost-effective robust solutions for system-on-chips.

This talk will first present the technology features, some market trends, main failure modes with phenomenological aspects and then original robust-by-design solutions acting at different levels.

Last but not least, circuit demonstrators will show that high performance and ultra-robustness can be both met in 28nm UTBB FDSOI CMOS.

FIDES programme

Charles Le Coz (Thales Global Services, Vélizy)

FIDES is a methodology for electronic systems reliability, based on physics of failure, taking into account all processes impacts on failure rate, from component selection to assembled board integration. An important advantage of FIDES methodology is the ability to describe precisely the life profile, in order to fit with actual applications (description of the different phases of the system missions). FIDES guide is not only a reliability prediction methodology, but also an engineering tool allowing the analysis of different extrinsic factors and the optimization of equipment designs. First FIDES guide, initiated by French MOD, was written in 2004, and a new revision has been published in 2010. Current study PISTIS will permit to update this guide in few years.

PISTIS programme

Jean-Claude Clément (Thales Group, Palaiseau, France)

The PISTIS project (ProgressIon deS Techniques de fiabIlité préviSionnelle) is driven by the French MOD and concerns the study of the reliability of components and advanced technologies. Different technologies will be studied: Deep-Sub-Micron components (FPGA, SDRAM-DDR3, Flash), microwave GaN and power transistors. The objective of this study is to define a new FIDES model for reliability. This project includes also a study and a comparison of the different accelerated stress tests for electronic equipment. The Pistis project started in September 2015 and the results are expected for end 2019. This presentation will include a presentation of the different planned methodologies, based on long-term tests, close of the real use conditions.


Eric Moreau, product & application director, Exagan

Exagan’s mission is to accelerate the transition of the power-electronics industry to smaller, more efficient and easier-to-use electrical converters, key components that are used in virtually all electronic devices. This can be accomplished by moving beyond silicon-based electronics to more advanced GaN-on-silicon technology. The solution lies in mastering the full GaN product flow, which requires expertise in material science, semiconductor device design, manufacturing and applications.

Exagan was co- founded by Frédéric Dupont and Fabrice Letertre, together with Soitec, world leader in generating and manufacturing revolutionary semiconductor materials and CEA-Leti, a leading European research center focused on micro- and nanotechnologies. By locating Exagan headquarter in the French Silicon Valley and the Product and Application Center of Expertize in Toulouse, Exagan is part of the unique Minatec campus and the associated miniaturization-technology clusters (Minalogic, Tenerrdis) and in very close collaboration with the key players providing Embedded E/E Systems for the aerospace, automotive and industrial markets.

Exagan develops the G-Stack™ material proprietary technology as the most effective solution to achieve the ultimate balance between high-quality, crack-free material, stress management and flat 200-mm wafers, enabling standardized manufacturing of GaN-on-silicon devices for applications up to 1,200 V. Fab lite business model provides Exagan with industrial partnerships for large-scale production of GaN devices at 200-mm silicon foundries to satisfy our customer’s needs for a robust supply of semiconductors qualified to secure high volume and high quality applications. 650-V and 1,200-V Exagan G-FET™ power switch product solutions are developed using Exagan proprietary G-Stack™ wafers. Backed by a robust supply chain of established silicon foundries and test companies, Exagan G-FET™ products exhibit extremely low conduction and switching losses, enabling very high operating frequencies. Equipped with such devices, customers will be able to rethink their systems and application roadmaps to achieve unprecedented system integration, efficiency levels and robustness.

The G-FET (650 V), Exagan’s first-generation product, will fit most customers’ requirements in IT electronics, automotive and solar applications. This product ranges from a few amperes to several tens of amperes, and is available as simple die or packaged devices with a novel known-good-die (KGD) capability that greatly reduces the integration risk in power modules.