Start date :16/11/2018
End date :16/11/2018
Time :9.30 am to 16.30 pm
Location : B612 Building - 3 rue Tarfaya, 31405, Toulouse
The IRT Saint Exupéry and the CNRS GDR SOC2 pursue their cooperation with the organization of the 2nd industrial and academic event related to Hardware interference and temporal determinism for modern SoC.
Modern SoCs based on multicore processors become more challenging to control when supporting critical embedded applications. We propose to investigate these new hardware platforms to satisfy safety properties such as timing determinism and freedom from interference.
The objective of this day is to gather the academic and industrial communities on embedded systems design, including researchers from the hardware and software domains. In this context, we propose to explore the configuration of hardware and software architectures in modern multicore SoCs, in order to support critical embedded applications. The new standards, constraints and challenges which system designers will have to face will be debated with a focus on timing determinism and freedom from interference characteristics of these modern hardware micro-architectures.
The day is organized around four main invited presentations and pitches/posters session based on CNRS/IRT team contributions selected by the organizing committee.
> Registration (mandatory) and venue <
Organization Committee:
Abstract: Multi-cores are problematic in real-time systems due to contention between memory accesses. Time Division Multiplexing (TDM) is a popular and predictable solution allowing to bound access latencies and reserve bandwidth. However, it is non-work-conserving and inefficient for resources with variable access latencies (e.g. DRAM), resulting in poor utilization. We present a TDM-based dynamic arbitration scheme that operates at the granularity of clock cycles instead of TDM slots by exploiting slack. The scheme preserves the guarantees of TDM in the worst case, while improving memory utilization on average.
Abstract: From a study of multi-core timing analysis state-of-the-art, we present a set of possible interferences in multi and many-core. We show how to take them into account in timing analysis and/or how to eliminate some interferences by a smart software implementation and hardware configuration. In our timing analysis, we schedule (time triggered) and estimate the worst-case response time for a data-flow application. We illustrate our study on the Kalray MPPA 2 platform.
Abstract: Hypervisors enable the instantiation of multiple virtual machines (VMs), making it possible to run applications in a single SoC. Timing properties are difficult to guarantee in such an environment as some resources, like processor core(s), caches, TLBs and the system bus, are inevitably shared between VMs. This talk classifies the various hypervisor approaches and identifies -from an embedded systems and real-time point of view- their useful as well their superfluous features. Approaches how to achieve determinism in theory are introduced and further analyzed for their practical applicability in the presence of, e.g. shared caches.
Abstract: Embedded systems have to run fast, but they also have to show the level of determinism required by verification, validation and certification processes. The dual objective of performance and determinism can only be achieved by appropriate combination of design and analysis techniques, both at hardware and software levels. In this talk, we will give an overview of the CAPHCA project currently on-going at IRT Saint Exupéry towards that goal, and present some of its results. We will consider the modelling and analysis of existing COTS SoCs, the design of deterministic-by-construct microarchitectures, and their programming using classical technologies such as OpenMP, or more specific synchronous programming approaches.
