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[Portrait 08] Nesrine Badache, R&D engineer in model-based systems engineering (MBSE)

IRT Saint Exupéry pursues a series of portraits devoted to the men and women who best represent the institute: its researchers. Their high-level skills and wealth of experience contribute hugely to IRT Saint Exupéry’s performance and unique position, which is so crucial for its members and partners.

Can you tell us about your career?

I wanted to become a doctor of pharmacy but gradually realised that I was attracted more by technology. My father, researcher and professor in computer science, encouraged me to follow his path, so I did a Master 2 in software engineering at USTHB[1]in Algiers. Then I was given a merit scholarship for a Master 2 in IT and telecommunications research at the University of Poitiers with ISAE-ENSMA[2].
Afterwards I did a PhD thesis at INPT-ENSEEIHT in the IRIT laboratory[3] on embedded real-time systems. My research works looked at temporal allocation in the sizing of IMA[4] architectures embedded in planes. I went from the conventional IT of a small computer to complex calculators that embed real-time critical IT! It was unimaginable for me at the time!


I went towards modelling complex systems (MBSE) when I became an R&D engineer at the Toulouse-based SMB Artal Technologies. My job was to help develop a method and tool for modelling and simulating complex systems for integration, verification and validation in the early design phases of avionics architectures. I also contributed to the IRT Saint Exupéry INGEQUIP project by modelling the system architecture of the Twirtee robot using the Capella tool. After two years, I joined CS GROUP in 2017 with a dual mission. I do MBSE expertise with CS Group customers to support their activities, from defining their needs to validating the systems, and I’m available part-time at IRT Saint Exupéry on the CAPHCA project.

Can you tell us more about the IRT Saint Exupéry CAPCHA project and the role you play in it?

The aim of CAPHCA[5] is to develop safe embedded real-time systems that exploit the new generation of architectures of computer hardware on the market, such as processors with multiple computational units called multi-cores, systems on a chip (SoC[6]) and FPGAs[7], types of electronic components integrated logic circuit that can be reconfigured after manufacture. It is an ambitious project that tackles a multitude of issues associated with multi-cores, which are the future of embedded computing in critical systems in the aeronautics, space and automotive sectors. Although these architectures offer very high performance levels, they do so at the expense of predictability, a property that is essential to critical systems and which is crucial for their certification.


CAPHCA pools several tools and methods – academic and industrial – which already exist or that have been developed in the project. These tools address various industrial problems, in a large chain of tools to consolidate expertise, observations and results. My contribution consists of modelling the entire tool chain to give a clear structure to a broad and disparate set of software components. It will facilitate their interconnection by improving the way the interfaces and exchanged data are controlled. What is more, it will highlight the relationship between operational needs and technological solutions. It is a transverse activity of consolidation and consistency. I have this opportunity to work with all the members of the team to understand their needs, whether in terms of software or hardware.

What results have been obtained?

The results of our work reflect the diversity of industrial challenges. We will deliver (i) a set of tools (worst case static analysis, an OpenMP[8] parallel software implementation tool in FPGA, a cache simulation tool, etc.); (ii) a hardware architecture (a deterministic multi-core processor) together with the resources to optimise it; (iii) extensions of existing tools (multi-core deployment tool); and finally (iv) the results of the evaluation. Although each result meets the need of a particular manufacturer, it also responds to the future needs of each of them. My modelling work will facilitate understanding of the solutions and their future exploitation via a model of these toolchains, such as a user guide. Numerous publications are associated with the work carried out as part of the project.


The final review is planned for December and the project will make way in 2020 for a further development, the scope of which is being defined with industrial partners.

What do you like at IRT Saint Exupéry?

The project has mobilised twenty or so people – engineers seconded by their company, researchers, post-docs and interns – who have different corporate cultures and different personalities. My transverse activity, which involves collecting information, means I have to communicate with them both from a technical and personal point of view and always with kindness. Despite the organisation, meaning that I have to be present on two different sites, and on several independent projects, it’s rewarding to feel part of two families of companies.

Do you have a small story to share with us?

I’m the only woman out of twenty people. It’s incredible but there aren’t any applicants in these areas! In Algiers, in computing, there were as many girls in this field. And, whether you are a girl or a boy, the demand for excellence is the same. During my study in Poitiers, out of 55 students, there were only three girls! Girls should be encouraged from an early age to feel confident in the engineering sector.


Publications CAPHCA project – ERTS 2020 (9)

[1] Université des Sciences et de la Technologie Houari Boumédiène, Algiers (Algeria)

[2] Ecole Nationale Supérieure de Mécanique et d’Aérotechnique, Groupe ISAE, Poitiers

[3] Institut de Recherche en Informatique de Toulouse (CNRS/INP Toulouse/Univ. Toulouse 3 Paul Sabatier/Uni. Toulouse 1 Capitole/Univ. Toulouse 2 Jean Jaurès). Thesis supervisors: Christian Fraboul and Jean-Luc Scharbarg, Katia Jaffres-Runser

[4] Integrated Modular Avionics

[5] Critical applications on predictable high-performance computing architecture

[6] System on a chip which may include memory, one or more microprocessors, interface peripherals or any other component needed to perform the expected function

[7] Field-Programmable Gate Arrays

[8] Open Multi-Processing: application programming interface (API) for parallel computing on shared memory architecture.

[9] ERTS 2020 – 10th European Congress on Embedded Real Time Software and Systems, 29-31 janvier 2020, Toulouse